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1 ? fn3072.7 icl7660, icl7660a cmos voltage converters the intersil icl7660 and icl7660a are monolithic cmos power supply circuits which offer unique performance advantages over previously available devices. the icl7660 performs supply voltage conversions from positive to negative for an input range of +1.5v to +10.0v resulting in complementary output voltages of -1.5v to -10.0v and the icl7660a does the same conver sions with an input range of +1.5v to +12.0v resulting in complementary output voltages of -1.5v to -12.0v. only 2 noncritical external capacitors are needed for the charge pump and charge reservoir functions. the icl7660 and icl7660a can also be connected to function as voltage doublers and will generate output voltages up to +18.6v with a +10v input. contained on the chip are a series dc supply regulator, rc oscillator, voltage level translator, and four output power mos switches. a unique logic element senses the most negative voltage in the device and ensures that the output n-channel switch source-substra te junctions are not forward biased. this assures latchup free operation. the oscillator, when unloaded, oscillates at a nominal frequency of 10khz for an input supply voltage of 5.0v. this frequency can be lowered by the addition of an external capacitor to the ?osc? terminal, or the oscillator may be overdriven by an external clock. the ?lv? terminal may be tied to ground to bypass the internal series regulator and improve low voltage (lv) operation. at medium to high voltages (+3.5v to +10.0v for the icl7660 and +3.5v to +12.0v for the icl7660a), the lv pin is left floating to prevent device latchup. pinouts icl7660, icl7660a (8 ld pdip, soic) top view features ? simple conversion of +5v logic supply to 5v supplies ? simple voltage multiplication (v out = (-) nv in ) ? typical open circuit voltage conversion efficiency 99.9% ? typical power efficiency 98% ? wide operating voltage range - icl7660 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5v to 10.0v - icl7660a . . . . . . . . . . . . . . . . . . . . . . . . . 1.5v to 12.0v ? icl7660a 100% tested at 3v ? easy to use - requires only 2 external non-critical passive components ? no external diode over full temp. and voltage range ? pb-free plus anneal available (rohs compliant) applications ? on board negative supply for dynamic rams ? localized processor (8080 type) negative supplies ? inexpensive negative supplies ? data acquisition systems nc cap+ gnd cap- 1 2 3 4 8 7 6 5 v+ osc lv v out data sheet october 10, 2005 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 1999-2004, 2005. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn3072.7 october 10, 2005 ordering information part number temp. range (c) package pkg. dwg. # icl7660cba* 7660cba 0 to 70 8 ld soic (n) m8.15 icl7660cbaz* (see note) 7660cbaz 0 to 70 8 ld soic (n) (pb-free) m8.15 icl7660cbaza* (see note) 7660cbaz 0 to 70 8 ld soic (n) (pb-free) m8.15 icl7660cpa 7660cpa 0 to 70 8 ld pdip e8.3 icl7660cpaz ( see note) 7660cpaz 0 to 70 8 ld pdip** (pb-free) e8.3 icl7660acba* 7660acba 0 to 70 8 ld soic (n) m8.15 icl7660acbaza* (see note) 7660acbaz 0 to 70 8 ld soic (n) (pb-free) m8.15 icl7660acpa 7660acpa 0 to 70 8 ld pdip e8.3 icl7660acpaz (see note) 7660acpaz 0 to 70 8 ld pdip** (pb-free) e8.3 icl7660aiba* 7660aiba -40 to 85 8 ld soic (n) m8.15 icl7660aibaza* (see note) 7660aibaz -40 to 85 8 ld soic (n) (pb-free) m8.15 *add ?-t? suffix to part number for tape and reel packaging. **pb-free pdips can be used for through hole wave solder proces sing only. they are not intended for use in reflow solder proces sing applications. note: intersil pb-free plus anneal products employ special pb-free material sets ; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. icl7660, icl7660a
3 fn3072.7 october 10, 2005 c absolute maximum rati ngs thermal information supply voltage icl7660 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5v icl7660a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0v lv and osc input voltage . . . . . . -0.3v to (v+ +0.3v) for v+ < 5.5v (note 2) . . . . . . . . . . . . . . (v+ -5.5v) to (v+ +0.3v) for v+ > 5.5v current into lv (note 2) . . . . . . . . . . . . . . . . . . . 20 a for v+ > 3.5v output short duration (v supply 5.5v) . . . . . . . . . . . . continuous operating conditions temperature range icl7660c, icl7660ac. . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c icl7660ai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c thermal resistance (typical, note 1) ja (c/w) jc (c/w) pdip package* . . . . . . . . . . . . . . . . . . 110 n/a soic package . . . . . . . . . . . . . . . . . . . 160 n/a maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering, 10s). . . . . . . . . . . . . 300c (soic - lead tips only) *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications icl7660 and icl7660a, v+ = 5v, t a = 25c, c osc = 0, test circuit figure 11 unless otherwise specified parameter symbol test conditions icl7660 icl7660a units min typ max min typ max supply current i+ r l = - 170 500 - 80 165 a supply voltage range - lo v l +min t a max, r l = 10k ? , lv to gnd 1.5 - 3.5 1.5 - 3.5 v supply voltage range - hi v h +min t a max, r l = 10k ? , lv to open 3.0 - 10.0 3 - 12 v output source resistance r out i out = 20ma, t a = 25c - 55 100 - 60 100 ? i out = 20ma, 0c t a 70c - - 120 - - 120 ? i out = 20ma, -55c t a 125c - - 150 - - - ? i out = 20ma, -40c t a 85c - - - - - 120 ? v + = 2v, i out = 3ma, lv to gnd 0c t a 70c - - 300 - - 300 ? v+ = 2v, i out = 3ma, lv to gnd, -55c t a 125c - - 400 - - - ? oscillator frequency f osc -10- -10-khz power efficiency p ef r l = 5k ? 95 98 - 96 98 - % voltage conversion efficiency v out ef r l = 97 99.9 - 99 99.9 - % oscillator impedance z osc v+ = 2v - 1.0 - - 1 - m ? v = 5v - 100 - - - - k ? icl7660a, v+ = 3v, t a = 25c, osc = free running, test circuit figure 11, unless otherwise specified supply current (note 3) i+ v+ = 3v, r l = , 25c - - - - 26 100 a 0c < t a < 70c - - - - - 125 a -40c < t a < 85c - - - - - 125 a output source resistance r out v+ = 3v, i out = 10ma - - - - 97 150 ? 0c < t a < 70c - - - - - 200 ? -40c < t a < 85c - - - - - 200 ? oscillator frequency (note 3) f osc v+ = 3v (same as 5v conditions) - - - 5.0 8 - khz 0c < t a < 70c ---3.0--khz -40c < t a < 85c ---3.0--khz icl7660, icl7660a
4 fn3072.7 october 10, 2005 functional block diagram voltage conversion efficiency v out eff v+ = 3v, r l = ---99-- % t min < t a < t max ---99-- % power efficiency p eff v+ = 3v, r l = 5k ? ---96-- % t min < t a < t max ---95-- % notes: 2. connecting any input terminal to voltages greater than v+ or less than gnd may cause destructive latchup. it is recommended t hat no inputs from sources operating from external supplies be ap plied prior to ?power up? of the icl7660, icl7660a. 3. derate linearly above 50c by 5.5mw/c. 4. in the test circuit, there is no external capacitor applied to pin 7. however, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, of the order of 5pf. 5. the intersil icl7660a can operate without an external diode over the full temperatur e and voltage range. this device will fun ction in existing designs which incorporate an external diode with no degradation in overall circuit performance. electrical specifications icl7660 and icl7660a, v+ = 5v, t a = 25c, c osc = 0, test circuit figure 11 unless otherwise specified (continued) parameter symbol test conditions icl7660 icl7660a units min typ max min typ max rc oscillator 2 voltage level translator voltage regulator logic network osc lv v+ cap+ cap- v out typical performance curves (test circuit of figure 11) figure 1. operating voltage as a function of temperature figure 2. output source resistance as a function of supply voltage 10 supply voltage range (no diode required) 8 6 4 2 0 -55 -25 0 25 50 100 125 temperature ( c ) supply voltage (v) 10k t a = 25 c 1000 100 10 01 23 4567 8 supply voltage (v+) output source resistance ( ? ) icl7660, icl7660a
5 fn3072.7 october 10, 2005 figure 3. output source resistance as a function of temperature figure 4. power conversion efficiency as a function of osc. frequency figure 5. frequency of oscillation as a function of external osc. capacitance figure 6. unloaded oscill ator frequency as a function of temperature figure 7. output voltage as a function of output current figure 8. supply current and power conversion efficiency as a function of load current typical performance curves (test circuit of figure 11) (continued) 350 300 250 200 150 100 50 0 -55 -25 0 25 50 75 100 125 temperature ( c ) output source resistance ( ? ) i out = 1ma v + = +2v v+ = 5v power conversion efficiency (%) t a = 25 c i out = 1ma i out = 15ma 100 98 96 94 92 90 88 86 84 82 80 100 1k 10k osc. frequency f osc (hz) v+ = +5v oscillator frequency f osc (hz) 10k 1k 100 10 v+ = 5v t a = 25 c 1.0 10 100 1000 10k c osc (pf) 20 18 16 14 12 10 8 6 -50 -25 0 25 50 75 100 125 oscillator frequency f osc (khz) temperature ( c ) v + = +5v t a = 25 c v+ = +5v 5 4 3 2 1 0 -1 -2 -3 -4 -5 output voltage load current i l (ma) slope 55 ? 0 1020304050607080 p eff i + t a = 25 c v + = +5v supply current i+ (ma) 100 90 80 70 60 50 40 30 20 10 0 100 90 80 70 60 50 40 30 20 10 0 0 102030405060 power conversion efficiency (%) load current i l (ma) icl7660, icl7660a
6 fn3072.7 october 10, 2005 detailed description the icl7660 and icl7660a contain all the necessary circuitry to complete a negative voltage converter, with the exception of 2 external capacitors which may be inexpensive 10 f polarized electrolytic types . the mode of operation of the device may be best understood by considering figure 12, which shows an idealized negative voltage converter. capacitor c 1 is charged to a voltage, v+, for the half cycle when switches s 1 and s 3 are closed. (note: switches s 2 and s 4 are open during this half cycle.) during the second half cycle of operat ion, switches s 2 and s 4 are closed, with s 1 and s 3 open, thereby shifting capacitor c 1 negatively by v+ volts. charge is then transferred from c 1 to c 2 such that the voltage on c 2 is exactly v+, assuming ideal switches and no load on c 2 . the icl7660 approaches this ideal situation more closely than existing non-mechanical circuits. in the icl7660 and icl7660a, the 4 switches of figure 12 are mos power switches; s 1 is a p-channel device and s 2 , s 3 and s 4 are n-channel devices. the main difficulty with this approach is that in integrating the switches, the substrates of s 3 and s 4 must always remain reverse biased with respect to their sources, but not so much as to degrade their ?on? resistances. in addition, at circuit start-up, and under output short circuit conditions (v out = v+), the output voltage must be sensed and t he substrate bias adjusted accordingly. failure to accomplish this would result in high power losses and probable device latchup. this problem is eliminated in the icl7660 and icl7660a by a logic network which senses the output voltage (v out ) together with the level translators, and switches the substrates of s 3 and s 4 to the correct leve l to maintain nece ssary reverse bias. figure 9. output voltage as a function of output current figure 10. supply current and power conversion efficiency as a function of load current note: 6. these curves include in the supply current that current fed directly into the load r l from the v+ (see figure 11). thus, approximately half the supply current goes directly to the positive side of the l oad, and the other half, through the icl7660/icl7660a, to the negativ e side of the load. ideally, v out 2v in , i s 2i l , so v in x i s v out x i l . note: for large values of c osc (>1000pf) the values of c 1 and c2 should be increased to 100 f. figure 11. icl7660, icl7660a test circuit typical performance curves (test circuit of figure 11) (continued) t a = 25 c v+ = 2v +2 +1 0 -1 -2 slope 150 ? 012345678 load current i l (ma) output voltage 100 90 80 70 60 50 40 30 20 10 0 power conversion efficiency (%) p eff i+ load current i l (ma) 0 1.5 3.0 4.5 6.0 7.5 9.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0 supply current (ma) (note 6) t a = 25 c v + = 2v 1 2 3 4 8 7 6 5 + - c 1 10 f i s v+ (+5v) i l r l -v out c 2 10 f icl7660 c osc + - (note) icl7660a icl7660, icl7660a
7 fn3072.7 october 10, 2005 the voltage regulator portion of the icl7660 and icl7660a is an integral part of the anti-latchup circuitry, however its inherent voltage drop can degrade operatio n at low voltages. therefore, to improve low voltage operation the ?lv? pin should be connected to ground, disabling the regulator. for supply voltages greater than 3.5v the lv terminal must be left open to insure latchup proof operati on, and prevent device damage. theoretical power efficiency considerations in theory a voltage converter can approach 100% efficiency if certain conditions are met. 1. the driver circuitry consumes minimal power. 2. the output switches have ex tremely low on resistance and virtually no offset. 3. the impedances of the pump and reservoir capacitors are negligible at the pump frequency. the icl7660 and icl7660a approa ch these conditions for negative voltage conversion if large values of c 1 and c 2 are used. energy is lost only in the transfer of charge between capacitors if a change in voltage occurs. the energy lost is defined by: e = 1 / 2 c 1 (v 1 2 - v 2 2 ) where v 1 and v 2 are the voltages on c 1 during the pump and transfer cycles. if the impedances of c 1 and c 2 are relatively high at the pump frequency (refer to figure 12) compared to the value of r l , there will be a substantial difference in the voltages v 1 and v 2 . therefore it is not only desirable to make c 2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for c 1 in order to achieve maximum efficiency of operation. do?s and don?ts 1. do not exceed maximum supply voltages. 2. do not connect lv terminal to ground for supply voltages greater than 3.5v. 3. do not short circuit the output to v+ supply for supply voltages above 5.5v for extended periods, however, transient conditions including start-up are okay. 4. when using polarized capacitors, the + terminal of c 1 must be connected to pin 2 of the icl7660 and icl7660a and the + terminal of c 2 must be connected to ground. 5. if the voltage supply driving the icl7660 and icl7660a has a large source impedance (25 ? - 30 ? ), then a 2.2 f capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2v/ s. 6. user should insure that the output (pin 5) does not go more positive than gnd (pin 3). device latch up will occur under these conditions. a 1n914 or similar diode placed in parallel with c 2 will prevent the device from latching up under these conditions. (anode pin 5, cathode pin 3). v out = -v in c 2 v in c 1 s 3 s 4 s 1 s 2 8 3 2 5 3 7 figure 12. idealized negative voltage converter figure 13a. configuration fig ure 13b. thevenin equivalent figure 13. simple negative converter 1 2 3 4 8 7 6 5 + - 10 f icl7660 v out = - v+ v+ + - 10 f icl7660a v+ + - r o v out icl7660, icl7660a
8 fn3072.7 october 10, 2005 typical applications simple negative voltage converter the majority of applications will undoubtedly utilize the icl7660 and icl7660a for generation of negative supply voltages. figure 13 shows typical connections to provide a negative supply negative (gnd) for supply voltages below 3.5v. the output characteristics of the circuit in figure 13a can be approximated by an ideal voltage source in series with a resistance as shown in figure 13b. the voltage source has a value of -v+. the output impedance (r o ) is a function of the on resistance of the internal mos switches (shown in figure 12), the switching frequency, the value of c 1 and c 2 , and the esr (equivalent series resistance) of c1 and c2. a good first order approximation for r o is: rsw, the total switch resistanc e, is a function of supply voltage and temperature (see the output source resistance graphs), typically 23 ? at 25c and 5v. careful selection of c 1 and c 2 will reduce the remaining terms, minimizing the output impedance. high value capacitors will reduce the 1/(f pump ? c 1 ) component, and low esr capacitors will lower the esr term. increasing the oscillator frequency will reduce the 1/(f pump ? c1) term, but may have the side effect of a net increase in output impedance when c 1 > 10 f and there is no longer enough time to fully charge the capacitors figure 14. output ripple figure 15. paralleling devices figure 16. cascading devices for increased output voltage a t 2 t 1 b 0 -(v+) v 1 2 3 4 8 7 6 5 icl7660 v+ c 1 icl7660a 1 2 3 4 8 7 6 5 icl7660 c 1 icl7660a r l + - c 2 ?n? ?1? 1 2 3 4 8 7 6 5 v+ 1 2 3 4 8 7 6 5 + - 10 f + - 10 f + - 10 f + - 10 f v out = - nv + icl7660 icl7660a ?n? icl7660 icl7660a ?1? r o ? 2(r sw1 + r sw3 + esr c1 ) + 2(r sw2 + r sw4 + esr c1 ) + 1 + esr c2 (f pump ) (c1) (f pump = f osc , r swx = mosfet switch resistance) 2 combining the four r swx terms as r sw , we see that: r o ? 2 (r sw ) + 1 + 4 (esr c1 ) + esr c2 (f pump ) (c1) r o ? 2(r sw1 + r sw3 + esr c1 ) + icl7660, icl7660a
9 fn3072.7 october 10, 2005 every cycle. in a typi cal application where f osc = 10khz and c = c 1 = c 2 = 10 f: r o ? 46 + 20 + 5 (esr c ) since the esrs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(f pump ? c 1 ) term, rendering an increase in switching frequency or filter capacitance ineffective. typical electrolytic capacitors may have esrs as high as 10 ?. r o/ ? 46 + 20 + 5 (esr c ) since the esrs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(f pump ? c 1 ) term, rendering an increase in switching frequency or filter capacitance ineffective. typical electrolytic capacitors may have esrs as high as 10 ?. output ripple esr also affects the ripple voltage seen at the output. the total ripple is determined by 2 voltages, a and b, as shown in figure 14. segment a is the voltage drop across the esr of c 2 at the instant it goes from being charged by c 1 (current flow into c 2 ) to being discharged through the load (current flowing out of c 2 ). the magnitude of this current change is 2 ? i out , hence the total drop is 2 ? i out ? esr c2 v. segment b is the voltage change across c 2 during time t 2 , the half of the cycle when c 2 supplies current to the load. the drop at b is l out ? t2/c 2 v. the peak-to-peak ripple voltage is the sum of these voltage drops: again, a low esr capacitor will reset in a higher performance output. paralleling devices any number of icl7660 and icl7660a voltage converters may be paralleled to reduce output resistance. the reservoir capacitor, c 2 , serves all devices while each device requires its own pump capacitor, c 1 . the resultant output resistance would be approximately: cascading devices the icl7660 and icl7660a may be cascaded as shown to produced larger negative multipli cation of the initial supply voltage. however, due to the finite efficiency of each device, the practical limit is 10 device s for light loads. the output voltage is defined by: v out = -n (v in ), where n is an integer repres enting the number of devices cascaded. the resulting output resistance would be approximately the weighted su m of the individual icl7660 and icl7660a r out values. changing the icl7660/icl7660a oscillator frequency it may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. this is achieved by overdriving the oscillator from an external clock, as shown in figure 17. in order to prevent possible device latchup, a 1k ? resistor must be used in series with the clock output. in a situation where the designer has generated the external clock frequency using ttl logic, the addition of a 10k ? pullup resistor to v+ supply is required. note that t he pump frequency with external clocking, as with internal clocking, will be 1 / 2 of the clock frequency. output transitions occur on the positive-going edge of the clock. it is also possible to increase the conversion efficiency of the icl7660 and icl7660a at low load levels by lowering the oscillator frequency. this reduces the switching losses, and is shown in figure 18. however, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (c 1 ) and reservoir (c 2 ) capacitors; this is overcome by in creasing the values of c 1 and c 2 by the same factor that the fre quency has been reduced. for example, the addition of a 100pf capacitor between pin 7 (osc) and v+ will lower the oscill ator frequency to 1khz from its nominal frequency of 10khz (a multiple of 10), and thereby necessitate a corresponding in crease in the value of c 1 and c 2 (from 10 f to 100 f). r o ? 2 (23) + 1 + 4 (esr c1 ) + esr c2 (5 ? 10 3 ) (10 -5 ) r o ? 2 (23) + 1 + 4 (esr c1 ) + esr c2 (5 ? 10 3 ) (10- 5 ) v ripple ? [ 1 + 2 (esr c2 ) ] i out 2 (f pump ) (c2) r out = r out (of icl7660/icl7660a) n (number of devices) 1 2 3 4 8 7 6 5 + - 10 f icl7660 v out v+ + - 10 f v+ cmos gate 1k ? icl7660a figure 17. external clocking icl7660, icl7660a
10 fn3072.7 october 10, 2005 positive voltage doubling the icl7660 and icl7660a may be employed to achieve positive voltage doubling using the circuit shown in figure 19. in this application, the pu mp inverter switches of the icl7660 and icl7660a are used to charge c 1 to a voltage level of v+ -v f (where v+ is the supply voltage and v f is the forward voltage drop of diode d 1 ). on the transfer cycle, the voltage on c 1 plus the supply voltage (v+) is applied through diode d 2 to capacitor c 2 . the voltage thus created on c 2 becomes (2v+) - (2vf) or twice the supply voltage minus the combined forward voltage drops of diodes d 1 and d 2 . the source impedance of the output (v out ) will depend on the output current, but for v+ = 5v and an output current of 10ma it will be approximately 60 ? . combined negative voltage conversion and positive supply doubling figure 20 combines the functions shown in figures 13 and figure 19 to provide negative voltage conversion and positive voltage doubling simultaneously. this approach would be, for example, suitable for generating +9v and -5v from an existing +5v supply. in this instance capacitors c 1 and c 3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors c 2 and c 4 are pump and reservoir respectively for the doubled positive voltage. there is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the fi nite impedance of the common charge pump driver at pin 2 of the device. voltage splitting the bidirectional characteristics can also be used to split a higher supply in half, as shown in figure 21. the combined load will be evenly shared between the two sides. because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the dev ice. by using this circuit, and then the circuit of figure 16, +15v can be converted (via +7.5, and -7.5) to a nominal -15v, although with rather high series output resistance ( ~ 250 ? ). regulated negative voltage supply in some cases, the output impedance of the icl7660 and icl7660a can be a problem, partic ularly if the load current varies substantially. the circuit of figure 22 can be used to overcome this by controlling the input voltage, via an icl7611 low-power cmos op amp, in such a way as to maintain a nearly constant output voltage. direct feedback is inadvisable, since the icl7660s and icl7660as output does not respond instantaneously to change in input, but only after the switching delay. the circuit shown supplies enough delay to accommodate the icl7660 and icl7660a, while maintaining adequate feedback. an increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5 ? to a load of 10ma. 1 2 3 4 8 7 6 5 + - v out v+ + - c 2 c 1 c osc icl7660 icl7660a figure 18. lowering oscillator frequency 1 2 3 4 8 7 6 5 v + d 2 c 1 c 2 v out = (2v+) - (2v f ) + - + - d 1 icl7660 icl7660a figure 19. positive volt doubler 1 2 3 4 8 7 6 5 v + d 1 d 2 c 4 v out = (2v+) - (v fd1 ) - (v fd2 ) + - c 2 + - c 3 + - v out = - (nv in - v fdx ) c 1 + - icl7660 icl7660a figure 20. combined negative voltage converter and positive doubler 1 2 3 4 8 7 6 5 + - + - 50 f 50 f + - 50 f r l1 v out = v+ - v- 2 v+ v - r l2 icl7660 icl7660a figure 21. splitting a supply in half icl7660, icl7660a
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3072.7 october 10, 2005 other applications further information on the operation and use of the icl7660 and icl7660a may be found in an051 ?principals and applications of the icl7660 and icl7660a cmos voltage converter?. 1 2 3 4 8 7 6 5 + - 100 f 100 f v out + - 10 f icl7611 + - 100 ? 50k +8v 100k 50k icl8069 56k +8v 800k 250k voltage adjust - + icl7660 icl7660a figure 22. regulating the output voltage 1 2 3 4 8 7 6 5 + - + - 10 f 16 ttl data input 15 4 10 f 13 14 12 11 +5v logic supply rs232 data output ih5142 1 3 +5v -5v icl7660 icl7660a figure 23. rs232 levels from a single 5v supply icl7660, icl7660a
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